1. Field of the Invention
The present invention generally relates to semiconductor devices, manufacturing methods of the semiconductor devices, and mounting methods of the semiconductor devices, and more specifically, to a wafer level chip size package type semiconductor device, a manufacturing method of the semiconductor device, and a mounting method of the semiconductor device.
2. Description of the Related Art
Conventionally, packaging of a semiconductor device is implemented for every semiconductor chip. However, recently and continuously, a wafer level chip size package has been suggested as a high density mounting package that is contributing to making the size of an electronic device small or making the weight of the electronic device light.
In the above-mentioned wafer level chip size package, an assembly process is applied at a semiconductor wafer state and plural chips are resin sealed in a lump so that a single package is made as the end product.
According to such a wafer level chip size package, a bump pitch can be minute at substantially the same size as a bare chip and plural semiconductor chips are packaged in a lump. Hence, there is an advantage in that the manufacturing steps or materials can be simplified.
FIG. 1 through FIG. 3 are first through third cross-sectional views showing a manufacturing method of a related art wafer level chip size package type semiconductor device. In FIG. 1 through FIG. 3, for convenience of explanation, only two semiconductor elements (semiconductor devices) among a lot of semiconductor elements (semiconductor devices) on a single semiconductor substrate are shown as an example.
A so-called a wafer process is applied to manufacturing the wafer level chip size package semiconductor device. An active element such as a transistor or a passive element such as a capacitive element is formed on a main surface of a semiconductor substrate 1 made of silicon (Si). Furthermore, a multilayer interconnection layer 2 is formed on the main surface of the semiconductor substrate (See FIG. 1-(a)). The active element and the passive element are mutually connected via the multilayer interconnection layer 2 so that an electronic circuit having a desirable function can be formed.
While a detailed structure is not shown in FIG. 1, the multilayer interconnection layer 2 is formed by stacking plural wirings made of aluminum (Al) or copper (Cu) via interlayer insulation layers. A material having a low dielectric constant, namely so-called Low-K material, is used as a material of the interlayer insulation layer so that capacitance formed between wirings can be reduced and speed of transmission of an electronic signal can be high.
Plural outside connection electrode pads 3 made of aluminum (Al) are provided on the multilayer interconnection layer 2. An inorganic insulation payer (passivation layer) 4 made of, for example, silicon oxide (SiO2) or silicon nitride (SiN) covers an external edge part of the electrode pad 3 and an upper surface of the multilayer interconnection layer 2.
Then, in order to protect a surface of the semiconductor element, an organic insulation layer 5 such as polyimide resin layer selectively covers an upper surface of the passivation layer 4 and an edge part of the passivation layer 4 on the electrode pad 3.
In addition, a wiring layer 6 made of copper (Cu) is selectively provided so as to extend from an exposed upper surface of the electrode pad 3 onto an upper surface of the organic insulation film 5.
An outside connection metal pole (post) 7 made of copper (Cu) is provided in the vicinity of an edge part of an extended part of the wiring layer 6 by a plating method (See FIG. 1-(b)).
Next, sealing resin 8 made of an epoxy group resin or the like is provided so that an upper surface of the sealing resin 8 reaches a position slightly lower than an upper end surface of the metal pole 7. Furthermore, a solder bump 9 having a substantially spherical shape, as an outside connection projection electrode, is provided on an upper part of the metal post 7 slightly projecting from an upper surface of the sealing resin 8 (see FIG. 2-(c)).
After that, for example, a dicing process using a dicing blade 10 is applied to the sealing resin 8, the multilayer interconnection layer 2, and the semiconductor substrate 1 so that pieces of the semiconductor devices 15 are obtained (See FIG. 2-(d)).
As a result of this, the semiconductor device shown in FIG. 3 is formed having a structure where the metal pole 7 is provided in the vicinity of the end part of the wiring layer 6 connected to the electrode pad 3 provided on the upper surface of the multilayer interconnection layer 2, the sealing resin 8 is provided on the organic insulation film 5 including the wiring layer 6, the upper surface of the metal pole 7 projects from the upper surface of the sealing resin 8, and the outside connection solder bump 9 is provided on the upper end surface of the projecting metal pole 7.
On the other hand, for example, Japanese Laid-Open Patent Application Publication No. 2000-277463 discloses a semiconductor device having a structure where an annular groove is formed around an active region of the semiconductor device and a semiconductor substrate is sealed with sealing resin with which the groove is filled so that moisture resistance of the semiconductor device is improved.
As discussed above, in the manufacturing process of the wafer level chip size package type semiconductor device 15, in a step shown in FIG. 2-(d), the multilayer interconnection layer 2 and the semiconductor substrate 1 are cut by the dicing blade 10 so that pieces of the semiconductor devices 15 are formed.
However, at the time of the dicing step, the multilayer interconnection layer including the interlayer insulation layer 2 made of an insulation material having a low dielectric constant may be broken. Because of this, in the environment of use of the semiconductor device 15, the breakage of the interlayer insulation layer 2 may further develop so that moisture may enter from a broken surface. This may cause degradation of properties of the semiconductor element so that reliability of the semiconductor device 15 may be decreased.
In order to solve the above-discussed problem, the technique disclosed in Japanese Laid-Open Patent Application Publication No. 2000-277463 may be applied to the semiconductor device 15.
As mentioned above, in the technique disclosed in Japanese Laid-Open Patent Application Publication No. 2000-277463, the annular groove formed around the active region of the semiconductor device is filled with the sealing resin. However, such a sealing resin does not have a sufficient adhesive force with the semiconductor substrate such as a silicon (Si) substrate. Because of this, even if a groove is formed in the insulation layer around a wiring region (circuit forming part) forming an electronic circuit together with the functional element formed on the semiconductor substrate and the groove is filled with the sealing resin, the sealing resin may be easily removed from an interface with the semiconductor substrate. Hence, it may not be possible to solve the above-discussed problem.